IPC-9641 : 2013

1 PURPOSE

1.1 Introduction

During the surface mount assembly process of an electronic package to a printed board through a reflow temperature profile, the flatness behavior of both the package and printed board are critical for the integrity of solder joint formation and reliability. While the deviation of the package from planarity during this process is critical, controlling the printed board flatness is equally important for preventing subsequent assembly-related issues, including open or bridging joints, which ultimately cause product failure. Board flatness is largely driven by a change in intrinsic properties through exposure to changes in temperature, with the final flatness state becoming a function of the entire temperature history or reflow profile and support boundary conditions. It is also driven by copper symmetry stack-up and metal pattern balancing. The worst-case deviation of the printed board from flatness may be at room temperature, peak temperature during reflow, or at any temperature in between. Therefore, printed board flatness must be characterized during the entire reflow thermal cycle, and not solely at room temperature at the beginning and end of the process. This document aims to provide guidance on methods and procedures for critically evaluating printed board flatness during a simulated temperature reflow cycle.

1.2 Scope

The purpose of this test method is to measure the shape and relative change in shape of a local area of interest (e.g., flip-chip ball grid array (FCBGA) land area) of printed boards through a range of temperatures typical during surface mount and through-hole builds of integrated circuit packages to printed boards. The use of shape measurements and relative changes in shape will depend on the specific application and interest of the user performing the measurement. This guideline differs from and does not supersede IPC-TM-650, Method 2.4.22, which is used for inspection of bow and/or twist of bare printed boards at room temperature.